With the continual improvement of semiconductor chip fabrication techniques, the number of devices which can be packed onto a semiconductor chip has increased greatly, while the size of the individual devices have decreased markedly. Today several million devices can be fabricated in a single--chip consider, for example, the mega-bit memory chips which are commonly used today in personal computers and in other applications. In such high-density chips, elements must be insulated properly in order to obtain good performance. The main purpose of element insulation techniques is to provide good insulation between the elements of the devices using smaller insulation area, to provide more space for more devices and their elements.
In the past, the so-called LOCal Oxidation of Silicon (LOCOS) technique has been widely used in the art of insulation of integrated circuit chips. According to this method, a thick oxide is grown as an insulating layer, to insulate the elements. FIGS. 1A to 1D demonstrate the prior art LOCOS technique. At first, a pad oxide layer 11 and then a silicon nitride layer 12 are formed on a silicon substrate 10. Those layers are patterned using lithography and etching techniques, yielding the structure shown in FIG. 1A. After that, impurities of a type to form channel-stop are implanted in the uncovered portion of the substrate 10, to form a channel stop implantation layer 13, as shown in FIG. 1B.
Referring to FIG. 1C, a thick field oxide 14 is formed by thermal oxidization. Since the oxidizing speed of silicon nitride is less than that of silicon, the silicon nitride layer 12 works like a mask against thermal oxidization, so the field oxide grows only where the substrate 10 is not covered by the silicon nitride layer 12. Finally, silicon nitride layer 12 is removed to obtain the isolation structure shown in FIG. 1D.
The above described conventional LOCOS technique has a number of disadvantages, which become rather unacceptable when attempting to apply this technique to the fabrication of sub-micron devices. First, the oxidization of silicon does not happen only in the vertical direction but also in the horizontal direction. As a result, a part of the field oxide grows under the adjacent silicon nitride layer 12 and lifts it up, as can be seen in FIG. 1C. This is termed the "bird's beak effect" by persons skilled in the art. Secondly, due to the stresses caused by the bird's beak effect, a part of nitride in the compressed regions of silicon nitride layer 12 diffuses to adjacent tensile strained regions at the interface of the pad oxide layer 11 and the substrate 10, and forms a silicon-nitride-like region 15. In later processing to form gate oxides, the gate oxides will be thinned due to the mask effect of the silicon-nitride-like layer 15. It is termed "white ribbon effect" because a white ribbon will appear at the edges of active regions under optical microscopes.
Additionally, because the volume of silicon dioxide is 2.2 times as large as that of silicon, the field oxide 14 protrudes from the surface of the silicon substrate 10, forming a non-recessed surface. Furthermore, the channel stop implantation layer 13 will diffuse laterally during the high temperature oxidation of the silicon used in forming the field oxide 14, which reduces the width of adjacent active regions. Decreasing the width of those active regions is a disadvantage when one is trying to scale down the dimensions of the device. Additionally, due to the lateral expansion of the field oxide 14 during oxidation, there is a lot of stress which occurs in the active region. Many crystalline defects are produced near the bird's beak regions, and result in an increase of junction leakage and a reduction of the reliability of the devices.
Many modified processes have been promoted to overcome the above-discussed disadvantages of LOCOS, such as: adding a spacer to reduce the bird's beak effect, adding a sacrificial oxide layer to solve the white-ribbon effect, or forming a trench before depositing field oxide layer to obtain a flat surface. Each of these suggestions solves some of the disadvantages of LOCOS, but they also increase the complexity of entire processes and, at the same time, and reduce production efficiency.
Trench isolation is another technique which has been utilized in an attempt to overcome the disadvantages of LOCOS. In this technique, which is now described with reference to FIG. 2, trenches 18 and 19 are etched on the silicon substrate 10 and then a field oxide layer 14 is deposited to fill the trenches, so as to form a recessed isolation layer. This technique uses chemical vapor deposition (CVD) to form the field oxide layer. The field oxide layer is deposited on the entire surface of the substrate, including in the trenches 18 and 19, and therefore further processing is needed to remove oxide from active regions. Furthermore, the field oxide does not only grow vertically from the bottom of the trenches, but also laterally from the sidewalls of the trenches, as can be seen in FIG. 2. Since a typical semiconductor chip would have numerous trenches of varying widths, when the comparatively narrow trenches have been filled up, the comparatively wide trenches have not been fully filled. If the deposition process is extended to fill the wide trenches, the field oxide formed in the narrow trenches will be too thick, causing a non-recessed surface to occur which, in turn, presents certain disadvantages during later processing, as is well known by those skilled in the art.
In building more and more compact integrated circuits, a Silicon-On-Insulator (SOI) technique is frequently used. Its structure mainly comprises a single-crystal silicon layer deposited on an insulator, usually thinner than 1 .mu.m. An insulated trench is formed which extends to the insulator, thereby forming insulated silicon islands on the insulator, where devices can be formed thereon with excellent insulation from devices on neighboring islands. Such an isolated structure is suitable for use in high speed, low power consumption, or high voltage applications. Furthermore, this structure is practicable for three-dimensional integrated circuits, to solve limitations associated with two-dimensional integrated circuits.